Generally, the technology of taking half (1/2) of voltage 1/2V.sub.DD of power source voltage V.sub.DD for the potential of the memory cell plate and the precharge potential of the bit line is used in a dynamic RAM (DRAM).
The 1/2V.sub.DD precharge method precharges the bit line pair (bit line/auxiliary bit line) to 1/2V.sub.DD beforehand, amplifies the slight change in the potential of the bit line or the bit auxiliary line connected to the memory via a sense amplifier according to the memory information of the target memory cell during the reading, pulls up one of the bit lines to "1" (V.sub.DD) and pulls down the other to "0" (V.sub.SS) according to the direction of the change (contents of the memory information), and there are the advantages that the time for pulling up or pulling down of the bit pair is shorter compared to the V.sub.SS precharge method and the V.sub.DD precharge method, and that sensing can be executed at high speed. Furthermore, when the bit line pair divided into the complementary voltages (V.sub.DD, V.sub.SS) are short circuited, both are automatically balanced to the middle level (1/2 level), so that there exists the advantage of being able to return to the precharge voltage easily. Also, according to the method of setting the potential of the memory cell plate to 1/2V.sub.DD, it is possible to control or relax the electric field applied to the insulation film to .+-.1/2 V.sub.DD whether the stored voltage of the memory cell is "1" (V.sub.DD) or "0" (V.sub.SS).
However, when the read operation of the data from the memory cell or the data write operation in the memory cell is insufficient, the potential of the bit line or the auxiliary bit line may become lower than V.sub.DD. When this happens, even if the bit line pair is short circuited in the 1/2V.sub.DD precharge method and the potential of both are balanced to the middle level, it does not return precisely to the precharge voltage (1/2V.sub.DD). Also, the memory cell plate voltage may fluctuate due to the noise, etc., within the memory circuit, and there is the risk that the data will become destroyed because it is maintained unstably with fluctuating memory cell plate voltage.
Therefore, conventionally, a 1/2V.sub.DD generating circuit which constantly outputs 1/2V.sub.DD has been provided, and the stabilized output voltage 1/2V.sub.DD was fed directly or indirectly (via a gate) to the bit line pair or the memory cell plate in this type of memory in order to handle fluctuations in the cell plate voltage, and the defects in the data reading operation from the memory cell or data writing operation to the memory cell, etc.
In FIG. 5 a circuit configuration of a conventional 1/2V.sub.DD generating circuit is shown. This 1/2V.sub.DD generating circuit comprises a reference voltage generating circuit 100 which includes four MOS transistors M1-M4 and an output circuit 102 composed of a pair of MOS transistors M5-M6.
In reference voltage generating circuit 100, the source terminal of p-type MOS transistor M1 is connected to power source voltage terminal 104 which provides power source voltage V.sub.DD, and the source terminal of n-type MOS transistor M4 is connected to ground terminal 106 which provides ground potential V.sub.SS. The gate terminal and drain terminal of n-type MOS transistor M2 are connected to the drain terminal of p-type MOS transistor M1, and the drain terminal and the gate terminal of p-type MOS transistor M3 are connected to the drain terminal of n-type MOS transistor M4. The gate terminal of p-type MOS transistor M1, the gate terminal of n-type MOS transistor M4, the source terminal of n-type MOS transistor M2, and the source terminal of p-type MOS transistor M3 are connected.
In output circuit 102, the drain terminal of n-type MOS transistor M5 is connected to power source voltage terminal 104, and the drain terminal of p-type MOS transistor M6 is connected to ground terminal 106. The source terminal of N-type MOS transistor M5 and the source terminal of P-type MOS transistor M6 are connected, and are also connected to output terminal 108. The gate terminal of n-type MOS transistor M5 is connected to the gate terminal of n-type MOS transistor M2 and the source terminal of p-type MOS transistor M1. The gate terminal of p-type MOS transistor M6 is connected to the gate terminal of p-type MOS transistor M3 and the drain terminal of n-type MOS transistor M4. n-type MOS transistor M5 has the same constitution as n-type MOS transistor M2 of reference voltage generating circuit 100 and has about the same threshold voltage V.sub.TN. p-type MOS transistor M6 has the same constitution as p-type MOS transistor M3 of reference voltage generating circuit 100 and has about the same threshold voltage V.sub.T P. Output terminal 108 is electrically connected to each memory cell plate and each bit line pair of the capacitive load circuit, for example, the memory array.
In the 1/2V.sub.DD generating circuit with this structure the circuit is designed so that first reference voltage 1/2V.sub.DD is obtained in node nP between p-type MOS transistor M3 and n-type MOS transistor M2 of reference voltage generating circuit 100. Thus, second reference voltage (1/2V.sub.DD +V.sub.TN) is obtained in the gate terminal of n-type MOS transistor M2, and third reference voltage (1/2V.sub.DD -V.sub.TP) is obtained at the gate terminal of p-type MOS transistor M2. N-type MOS transistor M2 and n-type MOS transistor M5, and p-type MOS transistor M3 and p-type MOS transistor M6 respectively constitute current mirror circuits, so that output voltage 1/2V.sub.DD, equal to first reference voltage 1/2V.sub.DD, is obtained in the node between n-type MOS transistor M5 and p-type MOS transistor M6, namely, at output terminal 108.
When the voltage level at output terminal 108 drops even slightly from 1/2V.sub.DD due to fluctuation in the external circuit such as the load circuit, etc., voltage V.sub.GS between the gate and source exceeds threshold voltage V.sub.TN N in n-type MOS transistor M5 of output circuit 102, and the transistor M5 turns on. Thus, the current flows into the load circuit from power source voltage terminal 104 through output terminal 108. The load circuit is capacitive, so that the potential of the load circuit rises with the current. When the output voltage level rises (is restored) to 1/2V.sub.DD, transistor M5 is turns off. Also, when the output voltage level rises even slightly from 1/2V.sub.DD, voltage V.sub.GS between the gate and the source exceeds threshold voltage V.sub.TP in p-type MOS transistor M6 of output circuit 102, and the transistor M6 turns on. Thus, current is led into ground terminal 106 from the load circuit via output terminal 108 and the potential of the load circuit drops. When the output voltage level drops (is restored) to 1/2V.sub.DD, transistor M6 turns off.
As noted above in the conventional 1/2V.sub.DD generating circuit one of the transistors M5 and M6 operates in the linear region because voltage V.sub.GS between the gate and the source of output transistors M5 and M6 changes with respect to the fluctuation in the output voltage, and sources current to the output terminal 108 side from the power source voltage or supplies current to ground terminal 106 from the output terminal 108 side to correct the fluctuation in the output voltage. However, the current which flows by turning MOS transistors M5 and M6 on in the linear region is small; thus, a long time is necessary to restore the output voltage level to the normal value (near 1/2V.sub.DD).
On the other hand, the integration of a DRAM has improved exponentially to 1M, 4M, 16M, 64M, . . . and even the number of bit line pairs activated at once in the refresh cycle has increased to a few K, a few tens of K, . . . , and there is a trend for the capacitance of the load circuit connected to the 1/2V.sub.DD generating circuit to increase further. The larger the capacitance of the load circuit, the greater the amount of current which must be supplied with respect to fluctuations in the output voltage. Also, the precharge time and the memory cycle are being decreased more as the integration of the DRAM is enhanced, so that greater speed is needed even in the voltage restoring operation. However, the conventional 1/2V.sub.DD generating circuit has a limit to the capacity of the current supplied in capacity and a speed of feeding as noted above and it is not suited to the requirements of large capacity DRAMs of the super mb class.
It is an object of this invention to provide a 1/2V.sub.DD generating circuit which greatly improves the capacity of the current supplied and the speed, and which can accommodate even large capacity DRAMs of the super mb class with sufficient margin.